The calendar below provides information on the course's lecture (L), recitation (R), quiz (Q), conference sessions (C) and project (P) sessions.

The last lecture or recitation is delivered 5 weeks before the end of the semester; after that date, class time is spent entirely on the final project.

L1 Introduction

Lab 1 out

Problem set 1 out

L2 Combinational logic
L3 Introduction to Verilog® - combinational logic
L4 Sequential building blocks
L5 Simple sequential circuits and Verilog®
L6 Finite-state machines and synchronization

Problem set 1 due

Problem set 2 out

L7 Memory basics and timing

Lab 1 checkoff and report due

Lab 2 (Traffic light FSM) out

R1 FSM examples, Verilog® lab 2 discussion
L8-L9 Arithmetic structures
R2 More FSM, memory, arithmetic

Problem set 2 due

Problem set 3 out

L10 Analog building blocks Lab 2 checkoff
L11 System integration issues and major/minor FSM

Lab 2 report due

Lab 3 (Memory tester) out

R3 VGA timing generation, block RAM/ROM
L12 Reconfigurable logic architecture
L13 Video Problem set 3 due
Q1 Quiz review

Lab 3 (Memory tester) checkoff - No detailed report due (see lab for details)

Lab 4 (Pong game) out

Q2 Quiz
L14 Project kickoff

Formation of project teams

Lab 4 intermediate checkoff (not graded) due two days after Ses #L14

L15 LSI integration and performance transformations
L16 Power dissipation in digital systems

Lab 4 checkoff due two days after Ses #L16

Project abstracts due five days after Ses #L16

Lab 4 report due five days after Ses #L16

C1 Proposal conference with TAs Bring project proposals for the proposal conference
C2 Proposal conference with TAs

Lab 2 revised report due nine days after Ses #L16 (part of CIM)

Bring project proposals for the proposal conference

P1-P2 Block diagram conference with TAs
P3 Project design presentation
P4 Project design presentation (cont.)
P5 Project design presentation (cont.)
P6 Project design presentation (cont.) Customized project checklist due (groups + staff)
P7-P11 Implement/Debug
P12 Implement/Debug (cont.)

Final project demonstrations and video taping due

Final project report due three days after Ses #P12